Toggle X15508


Statement
 

pdf   zip   verilog

html

A toggle is a 1-output circuit that changes state at every cycle. Design a toggle circuit that starts with the output being 0 and generates an alternating sequence of 1’s and 0’s, i.e., 010101010101…

Specification

module toggle (t, clk, rst); input clk, rst; output t;

Input

  • clk is the clock signal.
  • rst is the synchronous reset signal.

Output

  • t is the output that toggles at every cycle.
Information
Author
Jordi Cortadella
Language
English
Official solutions
Unknown. This problem is being checked.
User solutions
Verilog