Parity X16400


Statement
 

pdf   zip   verilog

html

Design a circuit that calculates the parity of an 8-bit input vector. The output of the circuit must be 0 if the input vector has an even number of zeros, otherwise the output must be 1.

Specification

module parity8(v, parity); input [7:0] v; output parity;

Input

  • v is the 8-bit input vector.

Output

  • parity indicates the parity of the input vector.
Information
Author
Jordi Cortadella
Language
English
Official solutions
Unknown.
User solutions
Verilog