4-bit counter X35277


Statement
 

pdf   zip   verilog

html

Design a circuit that implements a 4-bit counter (mod 16). The counter must start at zero after reset and increase the value at each cycle.

Specification

module counter4(count, clk, rst); input clk, rst; output [3:0] count;

Input

  • clk is the clock signal.
  • rst is the synchronous reset signal.

Output

  • count is the 4-bit output of the counter.
Information
Author
Jordi Cortadella
Language
English
Official solutions
Unknown.
User solutions
Verilog