Design a 2-input multiplexer in which the inputs are 4-bit wide.
The selection signal is called sel, whereas the two inputs
are called in0 and in1. The output will be in0 when sel=0
and in1 when sel=1.
Specification
module mux4(in0, in1, sel, out); input [3:0] in0, in1; input sel; output [3:0] out;
Input
Output