Fibonacci X95484


Statement
 

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Design a sequential circuit that generates the Fibonacci series. The circuit will represent the numbers with n bits and will generate the Fibonacci numbers mod  2n. At each cycle, a new number must be generated. The following waveform illustrates the behavior of the circuit.

The circuit must be designed to represent the numbers with 6 bits.

Specification

module fibonacci(clk, rst, fib); input clk, rst; output [5:0] fib;

Input

  • clk is the clock signal.
  • rst is the synchronous reset signal.

Output

  • fib is the Fibonacci number generated at each cycle.
Information
Author
Jordi Cortadella
Language
English
Official solutions
Unknown. This problem is being checked.
User solutions
Verilog